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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
Pin Description (continued)
PIN
23
24
26
27
29
30
31
32
33
34
40
41
43
44
45
47
48
—
NAME
GATEGND
GATEV DD
OPSAFE2
CS2+
CS2-
GATE2
GATE1
CS1-
CS1+
OPSAFE1
PGAOUT1
A2/N.C.
SCL
SDA/DIN
A1/DOUT
BUSY
DV DD
EP
FUNCTION
Gate-Drive Amplifier Ground
Gate-Drive Amplifier Supply Input
Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND.
Current-Sense Positive Input 2. CS2+ is the external sense resistor connection to the LDMOS 2
supply.
Current-Sense Negative Input 2. CS2- is the external sense resistor connection to the LDMOS 2
drain.
Channel 2 Gate-Drive Amplifier Output
Channel 1 Gate-Drive Amplifier Output
Current-Sense Negative Input 1. CS1- is the external sense resistor connection to the LDMOS 1
drain.
Current-Sense Positive Input 1. CS1+ is the external sense resistor connection to the LDMOS 1
supply.
Operating Safe Channel 1 Input. Drive OPSAFE1 high to clamp GATE1 to AGND.
Programmable-Gain Amplifier Output 1
I 2 C-Compatible Address 2. See the Digital Serial Interface section.
No Connection. Leave unconnected in SPI mode.
Digital Serial Clock Input
I 2 C-Compatible Serial Data Input/Output
SPI-Compatible Serial Data Input
I 2 C-Compatible Address 1. See the Digital Serial Interface section.
SPI-Compatible Serial Data Output
Device Busy Output. See the BUSY Output section
Digital Supply Input
Exposed Pad. Connect to AGND. Internally connected to analog ground.
16
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